Introductory description

ES3B2-15 Digital Systems Design

Module web page

Module aims

Outline syllabus

This is an indicative module outline only to give an indication of the sort of topics that may be covered. Actual sessions held may differ.

Recap of combinational and sequential circuits: gates, multiplexers, encoders, decoders, latches, D flip-flop, registers, shift registers.
Design with hardware description languages: (Verilog) module definitions, gate-level circuits, assign statements, behavioural combinational descriptions, behavioural synchronous descriptions.
Design flow and FPGA architecture: basic circuit synthesis, FPGA logic blocks, hard blocks, I/O, mapping to FPGA blocks, placement and routing, configuring FPGAs.
Testing digital circuits: basic Verilog testbenches, self-checking testbenches, file I/O for input/output vectors, testing strategies.
Arithmetic circuits: limits of ripple adders, carry-lookahead adders, multipliers, fixed-point data representation and resulting errors, floating point circuit complexity.
Timing and pipelining: basic combinational timing characteristics, timing of synchronous components, computing circuit timing performance, pipelining for improved performance, hazards, race conditions, and metastability.
Processors and I/O: basic structure of a processor and how this relates to performance, integrating peripherals over UART, SPI, I2C, and faster serial standards, computing data rates for these standards.

Learning outcomes

By the end of the module, students should be able to:

• Analyse how mathematics is performed in custom circuits, and how simple units can be combined to implement complex compute datapaths. [M1]
• Through the practical use of the Verilog hardware description language (HDL), consolidate understanding of the theory of combinational and sequential circuits and how these combine in the design of digital computing circuits. [M2,M3,M6,M12]
• Evaluate the digital design flow as currently practised professionally in industry, with reference to field programmable gate arrays, and at a more general level, to custom application specific integrated circuits. [M2,M3,M13]
• Devise a testing strategy and design a testbench that evidence some originality to evaluate the functional correctness of a circuit using the testing features of the Verilog HDL and a professional standard simulator. [M1,M2,M3,M5,M6]
• With the aid of appropriate information sources, demonstrate awareness of timing constraints, synchronisation and verification techniques using digital systems engineering [M4].
• Comunicate effectively the complexity and creativity of a hardware implementation on FPGA. This should consider application of health & safety, diversity, inclusion, cultural, societal, environmental and commercial matters, codes of practice and industry standards. [M5]
• Function effectively as an individual, and as a member or leader of a team. Evaluate effectiveness of own and team performance. [M16]

Indicative reading list

Reading lists can be found in Talis

Subject specific skills

Ability to conceive, make and realise a component, product, system or process.
Ability to be pragmatic, taking a systematic approach and the logical and practical steps necessary for, often complex, concepts to become reality.
Ability to seek to achieve sustainable solutions to problems and have strategies for being creative and innovative.

Transferable skills

Numeracy: apply mathematical and computational methods to communicate parameters, model and optimize solutions.
Apply problem-solving skills, information retrieval, and the effective use of general IT facilities.
Communicate (written and oral; to technical and non-technical audiences) and work with others.
Plan self-learning and improve performance, as the foundation for lifelong learning/CPD.
Exercise initiative and personal responsibility, including time management, which may be as a team member or leader.
Overcome difficulties by employing skills, knowledge and understanding in a flexible manner.