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Throughout the 2021-22 academic year, we will be prioritising face to face teaching as part of a blended learning approach that builds on the lessons learned over the course of the Coronavirus pandemic. Teaching will vary between online and on-campus delivery through the year, and you should read guidance from the academic department for details of how this will work for a particular module. You can find out more about the University’s overall response to Coronavirus at: https://warwick.ac.uk/coronavirus.

ES3B2-15 Digital Systems Design

Department
School of Engineering
Level
Undergraduate Level 3
Module leader
Suhaib Fahmy
Credit value
15
Module duration
10 weeks
Assessment
50% coursework, 50% exam
Study location
University of Warwick main campus, Coventry
Introductory description

ES3B2-15 Digital Systems Design

Module web page

Module aims

To introduce students to the principles and practice of designing digital electronic circuits, with a focus on field programmable gate array implementation, including the tool flow, architecture, testing, and design for performance.

Outline syllabus

This is an indicative module outline only to give an indication of the sort of topics that may be covered. Actual sessions held may differ.

Recap of combinational and sequential circuits: gates, multiplexers, encoders, decoders, latches, D flip-flop, registers, shift registers.
Design with hardware description languages: (Verilog) module definitions, gate-level circuits, assign statements, behavioural combinational descriptions, behavioural synchronous descriptions.
Design flow and FPGA architecture: basic circuit synthesis, FPGA logic blocks, hard blocks, I/O, mapping to FPGA blocks, placement and routing, configuring FPGAs.
Testing digital circuits: basic Verilog testbenches, self-checking testbenches, file I/O for input/output vectors, testing strategies.
Arithmetic circuits: limits of ripple adders, carry-lookahead adders, multipliers, fixed-point data representation and resulting errors, floating point circuit complexity.
Timing and pipelining: basic combinational timing characteristics, timing of synchronous components, computing circuit timing performance, pipelining for improved performance, hazards, race conditions, and metastability.
Processors and I/O: basic structure of a processor and how this relates to performance, integrating peripherals over UART, SPI, I2C, and faster serial standards, computing data rates for these standards.

Learning outcomes

By the end of the module, students should be able to:

  • Analyse how mathematics is performed in custom circuits, and how simple units can be combined to implement complex compute datapaths.
  • Through the practical use of the Verilog hardware description language (HDL), consolidate understanding of the theory of combinational and sequential circuits and how these combine in the design of digital computing circuits.
  • Evaluate the digital design flow as currently practised professionally in industry, with reference to field programmable gate arrays, and at a more general level, to custom application specific integrated circuits.
  • Devise a testing strategy and design a testbench to evaluate the functional correctness of a circuit using the testing features of the Verilog HDL and a professional standard simulator.
  • Reason about the performance of synchronous digital circuits, based on the timing of basic components, and how pipelining affects performance, and how this differs from measuring the performance of software running on processors.
Indicative reading list
  • D. M. Harris and S. L. Harris, Digital Design and Computer Architecture, 2nd ed., Morgan Kaufmann, 2013. ISBN 978-0123944245
  • S. Brown and Z. Vranseic, Fundamentals of Digital Logic with Verilog Design, 3rd ed., McGraw Hill, 2014. ISBN 978-0073380544
Subject specific skills

Ability to conceive, make and realise a component, product, system or process.
Ability to be pragmatic, taking a systematic approach and the logical and practical steps necessary for, often complex, concepts to become reality.
Ability to seek to achieve sustainable solutions to problems and have strategies for being creative and innovative.

Transferable skills

Numeracy: apply mathematical and computational methods to communicate parameters, model and optimize solutions.
Apply problem-solving skills, information retrieval, and the effective use of general IT facilities.
Communicate (written and oral; to technical and non-technical audiences) and work with others.
Plan self-learning and improve performance, as the foundation for lifelong learning/CPD.
Exercise initiative and personal responsibility, including time management, which may be as a team member or leader.
Overcome difficulties by employing skills, knowledge and understanding in a flexible manner.

Study time

Type Required
Lectures 20 sessions of 1 hour (13%)
Practical classes 7 sessions of 2 hours (9%)
Other activity 2 hours (1%)
Private study 114 hours (76%)
Total 150 hours
Private study description

Guided independent learning: 114 hrs

Other activity description

2x1h Revision Classes

Costs

No further costs have been identified for this module.

You must pass all assessment components to pass the module.

Students can register for this module without taking any assessment.

Assessment group C
Weighting Study time
Design Assessment 50%

Assessed Design Assignment to design and implement a digital circuit of moderate complexity using the skills learnt in the course (10 pages report).

Online Examination 50%

qmp

~Platforms - QMP


  • Online examination: No Answerbook required
  • Students may use a calculator
  • Engineering Data Book 8th Edition
Feedback on assessment

Detailed marking on assessed design exercise.
Model solutions are published for past examination papers
Cohort level feedback on examinations

Past exam papers for ES3B2

Pre-requisites

To take this module, you must have passed:

Post-requisite modules

If you pass this module, you can take:

  • ES4F3-15 High Performance Embedded Systems Design

Courses

This module is Core for:

  • Year 3 of UESA-H634 BEng Electronic Engineering
  • Year 3 of UESA-H63W BEng Electronic Engineering
  • Year 4 of UESA-H63V BEng Electronic Engineering with Intercalated Year
  • Year 3 of UESA-H635 MEng Electronic Engineering
  • Year 3 of UESA-H63X MEng Electronic Engineering
  • UESA-H636 MEng Electronic Engineering with Intercalated Year
    • Year 3 of H636 Electronic Engineering with Intercalated Year
    • Year 4 of H636 Electronic Engineering with Intercalated Year
  • Year 3 of UESA-H605 Undergraduate Electrical and Electronic Engineering
  • Year 3 of UESA-H606 Undergraduate Electrical and Electronic Engineering MEng
  • Year 4 of UESA-H607 Undergraduate Electrical and Electronic Engineering with Intercalated Year

This module is Core optional for:

  • UESA-H636 MEng Electronic Engineering with Intercalated Year
    • Year 3 of H636 Electronic Engineering with Intercalated Year
    • Year 4 of H636 Electronic Engineering with Intercalated Year
  • Year 4 of UESA-H63Y MEng Electronic Engineering with Intercalated Year
  • Year 3 of UESA-H115 MEng Engineering with Intercalated Year
  • UESA-H607 Undergraduate Electrical and Electronic Engineering with Intercalated Year
    • Year 3 of H607 Electrical and Electronic Engineering with Intercalated year
    • Year 4 of H607 Electrical and Electronic Engineering with Intercalated year

This module is Optional for:

  • Year 3 of UESA-H113 BEng Engineering
  • Year 3 of UESA-H114 MEng Engineering
  • Year 4 of UESA-H109 MEng Engineering with Intercalated Year
  • Year 4 of UESA-H115 MEng Engineering with Intercalated Year

This module is Option list A for:

  • Year 3 of UESA-H106 BEng Engineering
  • Year 4 of UESA-H111 BEng Engineering with Intercalated Year
  • Year 4 of UESA-H118 BEng Engineering with Intercalated Year
  • Year 3 of UESA-H112 BSc Engineering
  • Year 3 of UESA-H107 MEng Engineering
  • Year 3 of UESA-H109 MEng Engineering with Intercalated Year