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ES4F3-15 High Performance Embedded Systems Design

School of Engineering
Undergraduate Level 4
Module leader
Eduardo Wachter
Credit value
Module duration
10 weeks
50% coursework, 50% exam
Study location
University of Warwick main campus, Coventry
Introductory description

ES4F3-15 High Performance Embedded Systems Design.

Module web page

Module aims

To develop a student’s ability in digital design to the level of designing high performance software/hardware embedded systems using hybrid FPGA reconfigurable devices combining processors and reconfigurable hardware fabric.

Outline syllabus

This is an indicative module outline only to give an indication of the sort of topics that may be covered. Actual sessions held may differ.

Design Flow and Verilog Recap: Revision of Register Transfer Level (RTL) design, behavioural modelling, hardware synthesis and implementation flow.

Design Space Exploration: Understanding area, performance, and power in the context of embedded systems, and the trade-offs between them.

High Level Synthesis: C-to-gates and other languages, compiler outline, supported language features, basic scheduling.

Interconnect and Data Movement: Processor to logic interfacing, busses and crossbars, networks-on-chip, Direct Memory Access (DMA).

Modern Hybrid FPGA Architecture: Advanced DSP block architecture, advanced I/O, partial reconfiguration, hybrid FPGA architecture, PCIe-connected FPGAs.

Accelerating Algorithms: Standard DSP structures, including FIR filters, image filters, number representation and numerical precision.

Learning outcomes

By the end of the module, students should be able to:

  • Apply advanced features of FPGA architectures in high performance embedded systems design. (M2,M12)
  • Design a hardware accelerator for a complex algorithm by evaluating its parallelism and arithmetic requirements. (M2)
  • Understand how to integrate a hardware accelerator with a processor and design the necessary software and hardware communication infrastructure. (M6,M12)
  • Apply specialist practical knowledge of hardware design at the register transfer level and understand the principles of high level synthesis. (M2,M4,M6,M12)
  • Understand the trade-offs between performance, area, and power in critiquing the design of accelerators.
  • Communicate effectively the complexity and creativity of a hardware-software co-design implementation on FPGA.
Indicative reading list

Embedded Systems Design with FPGAs, P Athanas, D. Pnevmatikatos, N. Sklavos (Editors), Springer, 2013.

Embedded Systems Fundamentals with Arm Cortex-M based Microcontrollers, A. G. Dean, Arm Education Media UK, 2017.

The Zynq Book: Embedded Processing with the ARM® Cortex-A9 on the Xilinx Zynq-7000 All Programmable SoC, Louise H. Crockett, Ross A. Elliot, Martin A. Enderwitz, Robert W. Stewart, Strathclyde Academic Media, 2014

Parallel Programming for FPGAs, R. Kastner, J. Matai, and S. Neuendorffer, arXiv, 2018.

Subject specific skills

Ability to conceive, make and realise a component, product, system or process
Ability to be pragmatic, taking a systematic approach and the logical and practical steps necessary for, often complex, concepts to become reality

Transferable skills

Communicate (written and oral; to technical and non-technical audiences) and work with others
Exercise initiative and personal responsibility, including time management, which may be as a team member or leader
Overcome difficulties by employing skills, knowledge and understanding in a flexible manner

Study time

Type Required
Lectures 10 sessions of 1 hour (7%)
Seminars 10 sessions of 1 hour (7%)
Practical classes 7 sessions of 2 hours (9%)
Other activity 2 hours (1%)
Private study 114 hours (76%)
Total 150 hours
Private study description

114 Private Study Hours

Other activity description

2x 1 hour revision classes.


No further costs have been identified for this module.

You must pass all assessment components to pass the module.

Assessment group C3
Weighting Study time
Design Assignment 50%

Design assignment (10 pages)

Online Examination 50%

QMP online examination

~Platforms - AEP,QMP

  • Online examination: No Answerbook required
  • Students may use a calculator
  • Engineering Data Book 8th Edition
Feedback on assessment
  • Support through office hours.
  • Detailed marking on assessed design assignment.
  • Cohort-level feedback on final exam.

Past exam papers for ES4F3


To take this module, you must have passed:


This module is Core for:

  • Year 4 of UESA-H63X MEng Electronic Engineering
  • Year 5 of UESA-H63Y MEng Electronic Engineering with Intercalated Year

This module is Optional for:

  • Year 4 of UESA-H606 Undergraduate Electrical and Electronic Engineering MEng
  • Year 5 of UESA-H607 Undergraduate Electrical and Electronic Engineering with Intercalated Year